An exemplary structure of typical phase interpolator is shown in FIG. 6. The phase interpolator is adapted to output in response to a control signal, output signals each having a phase corresponding to any of phases which are obtained by dividing the difference in phase between two input signals. A configuration is shown in FIG. 6 in which the phase difference between two input signals is divided into four regions, so that output signals corresponding to any of phases are output in response to a control signal.
Referring now to FIG. 6, the phase interpolator comprises a first differential pair of transistors (NMOS transistor pair MN31, MN32) to which first differential input signals (phase 0°) (CIB 0, CIT 0) are input as differential inputs; and second differential transistor pair (NMOS transistor pair MN33, MN34) to which second differential input signals (phase 90°) (CIB 90, CIT 90) are input as differential inputs. The output pairs of the first transistor pair (MN31, MN32) and second transistor pair (MN33, MN34) are commonly connected to each other and are connected to load resistors (also referred to as “output resistors”) (R1, R2) and are connected to differential terminals (OUTB, OUTT). The interpolator further comprises first to fourth current sources (NMOS transistors MN1 through MN4). The gates of the NMOS transistors MN1 through MN4 which constitute the first through fourth current sources are commonly connected to the gate of an NMOS transistor MN0 having its drain and gate which are connected to a constant current source I1 and its source which is grounded for forming a current mirror. In the foregoing description, the currents from the first through fourth current sources (MN1 through MN4) are mirror currents equal to a drain current of the NMOS transistor MN0. Weights may be assigned to the currents from the first through fourth current sources (MN1 through MN4). Although the first to fourth current sources (MN1 to MN4′) are illustrated in FIG. 6, it is to be noted that the number of current sources is not limited to only 4.
The phase interpolator further comprises first to fourth switch pairs (MN11, MN21), (MN12, MN22), (MN13, MN23), (MN14, MN24), comprising NMOS transistor pairs having their sources which are connected to first through fourth current sources (MN1 through MN4). The transistors MN11, MN12, MN13, MN14 on one side of the first through fourth switch pairs have their drains which are commonly connected to common sources of the first differential pair (MN31, MN32). The transistors MN21, MN22, MN23 and MN24 on the other side of the first to fourth switch pairs have their drains which are commonly connected to the common sources of the second differential pairs (MN33, MN34).
Control signals (PICT0, PICT1, PICT2, PICT3) are connected to the gates of the transistors MN11, MN12, MN13, MN14 on the side of the first through fourth switch pairs, respectively. Control signals (PICB0, PICB1, PICB2, PICB3) which are obtained by inverting the control signals (PICT 0 through 3) by an inverter INV are connected to the gates of the transistors MN21, MN22, MN23, MN24 on the other side of the first through fourth switch pairs. The first through fourth switch pairs are controlled so that one switch of the switch pair is turned on while the other switch is turned off.
The phase differences between two differential input signals (CIT0, CIB0), (CIT90, CIB90) are divided by controlling turning on or off of the transistor pairs of the first through fourth switch pairs (MN11, MN21), (MN12, MN22), (MN13, MN23), (MN14, MN24) with a four-bit control signal PIC [3:1] (the control signals PICT0, PICT1, PICT2, PICT3 are denoted by PIC [3:0] in FIG. 6) (provided that one of pair transistors is turned on when the other transistor is turned off) to change drive currents for first and second differential pairs (MN31, MN32), (MN33, MN34).
For example, when (PICT0, PICT1, PICT2, PICT3)=(1, 1, 1, 1), thus (PICB0, PICB1, PICB2, PICB3)=(0, 0, 0, 0), a drive current (a sum of the currents from the current sources MN1, MN2, MN3, MN4) is supplied to only common sources of the first differential pair (MN31, MN32), so that the differential output signal having a phase corresponding to the differential input signals (CIT0, CIB0) is output. When (PICB0, PICB1, PICB2, PICB3)=(1, 1, 1, 1), (PICT0, PICT1, PICT2, PICT3)=(0, 0, 0, 0), a drive current (a sum of currents from the current sources MN1, MN2, MN3, MN4) is supplied to only common sources of the second differential pair (MN33, MN34), so that the differential output signal having a phase corresponding to the differential input signals (CIT90, CIB90) having a phase difference of 90° is output. In case of other combination of control signals PICs [3:0], the differential output signal corresponding to a phase which is obtained by dividing the phase difference between the differential input signals (CIT0, CIB0) and (CIT90, CIB90) is output.
That is, output signals which are phase-out-of 22.5° are generated by inputting input signals of 0° and 90° and by variably controlling the weights assigned to four current sources (MN1, MN2, MN3, MN4). For example, by letting (PICT0, PICT1, PICT2, PICT3)=(1,0,0,0) and (PICB0, PICB1, PICB2, PICB3)=(0, 1, 1, 1), the common sources of the first differential transistor pair (MN31, MN32) are connected to the current source MN1 through a transistor MN11 which is turned on and the common sources of the second transistor pair (MN33, MN34) are connected to the current sources MN2, MN3, MN4 through the transistors MN22, MN23, MN24 which are turned on. Therefore, the ratio of a drive current (a current from the current source MN1) of the first differential transistor pair (MN31, MN32) to which a 0° clock is input to a drive current (a sum of the currents from the current sources MN2, MN3, MN4) of the second differential transistor pair (MN33, MN34) to which 90° clock is input is 1:3. A clock of 67.5° which is obtained by proportionally dividing an angle between 0° and 90° at a ratio of 1:3 is output.
In such a manner, current paths through a plurality of current sources are normally turned on in the phase interpolator during usual operation. (The MNOS transistors on one side of the first to fourth switch pairs are turned on while the others are turned off). No determination whether individual transistors constituting current sources are turned on or off can be made. In other words, operation of each one of a plurality of current sources can not be confirmed, individually.